The outcome of this workshop will provide future guidance on the shortage of IC design engineers in the US and training a future workforce. In particular, the workshop will examine industry and academic needs to find the appropriate pathway for the revitalization of IC research and education in the US.
Semiconductor ICs are an essential component of nearly every commercial product, from automobiles to electronic toothbrushes. Society benefits from increased productivity and quality of life through advancements in these products. However, we are also becoming increasingly dependent on other countries to manufacture such goods and increasingly for the development and design of them or the hiring of H1B visa holders to work in the US and design them. Training a domestic workforce to design such products is necessary for economic independence and growth but also for the security and stability of the US.
Chip design at US universities blossomed on account of the Mead and Conway Revolution (Conway). In 1978-79, Carver Mead and Lynn Conway wrote the seminal textbook Introduction to VLSI Systems (Mead). This book offered abstractions that transformed digital chip design from a complex physics problem into a much easier computer science problem and popularized chip design in academia. Conway also taught a VLSI course at MIT in 1978 leading to the Multi-Project Chip concept, and Danny Cohen established the Metal Oxide Semiconductor Implementation Service (MOSIS) at USC for VLSI prototyping. MOSIS fabricated free chips for university VLSI classes, initially with NSF support and later with profits from their commercial operations, but ceased offering this service in 2020. DARPA also kicked off a VLSI research project in 1980, popularizing Mead & Conway’s work and encouraging the development of chips and electronic design automation (EDA) tools.
Chip design was further fueled by a collaboration of universities and industry. Much early design was done with the MOSIS layout tool, but more advanced design requires synthesis and placement & routing tools. EDA vendors, including Cadence, Synopsys, and Mentor Graphics, established university programs with discounted tools. North Carolina State University developed the NCSU Process Design Kit (PDK) with modern predictive (i.e., non-fabricable) technology files (“FreePDK”). Through the 1990s, universities taught large VLSI classes at the graduate or advanced undergraduate level using a vibrant set of textbooks. Fabricating a chip through MOSIS and testing it became a rite of passage for thousands of engineering majors. Brunvand provided a cookbook to install and configure CAD tools and models for chip design with industry-standard tools on readily available processes (Brunvand). Flows became mature enough to be accessible to all university students.
In recent years, VLSI education has faced a decline leading to VLSI classes now offered only as a niche topic. According to faculty on a recent NSF-organized panel discussion, enrollments have dropped at most universities and the fraction of underrepresented students in these courses is close to zero at some schools. Textbook sales have sharply declined and predominantly moved to India and China. MOSIS has dropped support for the old 0.6-micron process long-used for class projects and dropped class funding entirely. The cost of discounted VLSI CAD tools is significantly higher than other university software and the cost per student increases when enrollments decline. The cost of maintaining these tools and their computing infrastructure also requires IT staffing and expertise as well as dedicated computer systems for licensing and installation.
VLSI research in academia has become very difficult because results using antiquated processes are generally not publishable and the design files (device models, design rules, and libraries) for advanced processes are proprietary and available only to faculty with special industry connections. Often universities are unwilling to sign the Non-Disclosure Agreements (NDAs) that some industrial partners require due to numerous restrictions on IP ownership, export control, liability, and other challenges. The cost of fabrication in advanced processes is also so high that it often requires piggybacking on an existing shuttle run from a corporate sponsor, again only available to faculty with special connections. Altogether, far fewer students are graduating from US universities who are prepared for careers in chip design.
The US is now facing both an economic and national security threat in the semiconductor industry. There is presently a worldwide semiconductor shortage that forced Apple to delay the iPhone 12 by two months (“Apple unveils new 5G iPhone 12 line in multiple sizes”) and cost the automotive industry a forecasted $60B in revenue (“How Covid led to a $60 billion global chip shortage for the auto industry”). In 2014, Broadcom found itself unable to compete in the cell phone application processor market against foreign competition from Samsung and MediaTek, closed the entire division, and was weakened to the point that it was acquired by a Singapore company, Avago (“Avago Technologies to Acquire Broadcom for $37 Billion”). There is a multibillion-dollar black market in counterfeit electronics and an estimated 15% of spare electronic parts purchased by the US Defense Department are counterfeit, threatening both reliability and security (“Senate Hearing 112-340”). In 2020, the Federal Communications Commission designated Chinese telecommunication firms Huawei and ZTE as national security threats because of the risk of espionage through their 5G networking equipment (“F.C.C. Designates Huawei and ZTE as National Security Threats”). The Chinese National Integrated Circuit Plan seeks to develop leading-edge domestic integrated circuit manufacturing capability by 2030, and the country invested $150B in its industry between 2014 and 2020 (“Can China Become the World Leader in Semiconductors?”). In 2014, IBM sold their chip business to Global Foundries, ending a source of domestic chip manufacturing.
Several forces are coming together with prospects to revitalize the US semiconductor industry. In March 2021, Intel CEO Pat Gelsinger announced a $20B investment to build two new IC fabrication plants in Arizona for 7 nm manufacturing and to sell foundry services to outside customers (“IDM 2.0 is the Powerful Combination of Intel’s Internal Factory Network, Third-party Capacity and New Intel Foundry Services”). This will significantly expand US manufacturing capacity. President Biden’s “American Jobs Plan” of March 2020 calls for over $50B investment in domestic chip manufacturing (“Biden plans to connect every American to broadband in new infrastructure package”). The elephant in the room, however, how we will educate and establish a workforce to create designs for manufacturing in these fabs.
There has been a significant interest in how open-source hardware designs and EDA tools can impact IC design, which has been notoriously closed-source. DARPA has funded broadly the development of an entirely open-source toolchain (“UC San Diego Selected to Lead Development of Open-Source Tools for Hardware Design Automation”), and open-source FPGA tool flows have also seen very mature toolchains for multiple FPGA architectures (“SymbiFlow”). DARPA has also funded the Electronic Resurgence Initiative to secure the supply chain and promote integrated circuit research and development (“DARPA Chip Effort Pivots to Securing US Supply Chain”). The Free and Open Source Silicon Foundation (FOSSi) is promoting open-source EDA tools and libraries (“FOSSi”). Industry consortiums such as CHIPS Alliance have coalesced around such open-source opportunities (“CHIPS Alliance”). Google has recently begun sponsoring Skywater Multi-Project Wafer shuttles for any open-source project in older 180nm technologies and may expand to more recent, but still older, technologies (“Google Partners with SkyWater and Efabless to Enable Open Source Manufacturing of Custom ASICs”). One monumental success in the open-source area has been the adoption of RISC-V by numerous companies and academic institutions (“RISC-V grows globally as an alternative to Arm and its license fees”). Entire microprocessor ecosystems, which were once filled with proprietary ISAs, firmware, and compilers, are now freely available and competitive in performance.
While the Mead-Conway revolution began by moving IC design from analog designers to digital designers, the open-source movement may enable a shift from digital designers to software engineers for the next generation of “IC designers”. Hardware design has benefitted from many software design efficiency and productivity paradigms such as high-level synthesis, intermediate representations, programming languages, formal verification, etc. Recently, for example, new high-level design languages such as Chisel have started to change how we abstract hardware design and offer new opportunities for optimization and integration (“Chisel/FIRRTL Hardware Compiler Framework”). Improved accessibility of open-source IC design ecosystems opens the opportunity for innovation as well as a chance to increase diversity by stretching the concept of who can be an IC designer.
As Moore’s law diminishes, it is even more critical that universities reconsider their approach to IC education and research. Improvements in IC designs will need to come from new devices with disparate technologies, improvements in EDA toolchains and methodologies, and integration of heterogeneous systems. All of these will require rethinking both how we design to address the complexity and how we revitalize student interest in hardware systems. Academics and industry must address this change now when training our future workforce.